Allwinner A80 Display Engine Clock Control Binding
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Required properties :
- compatible: must contain one of the following compatibles:
		- "allwinner,sun9i-a80-de-clks"

- reg: Must contain the registers base address and length
- clocks: phandle to the clocks feeding the display engine subsystem.
	  Three are needed:
  - "mod": the display engine module clock
  - "dram": the DRAM bus clock for the system
  - "bus": the bus clock for the whole display engine subsystem
- clock-names: Must contain the clock names described just above
- resets: phandle to the reset control for the display engine subsystem.
- #clock-cells : must contain 1
- #reset-cells : must contain 1

Example:
de_clocks: clock@3000000 {
	compatible = "allwinner,sun9i-a80-de-clks";
	reg = <0x03000000 0x30>;
	clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
	clock-names = "mod", "dram", "bus";
	resets = <&ccu RST_BUS_DE>;
	#clock-cells = <1>;
	#reset-cells = <1>;
};
